Paper Title :Energy Efficient Finfet Based SRAM Design in 22-Nanometer Technology
Author :Ayushi Gagneja, Rajesh Mehra
Article Citation :Ayushi Gagneja ,Rajesh Mehra ,
(2017 ) " Energy Efficient Finfet Based SRAM Design in 22-Nanometer Technology " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 14-20,
Volume-5,Issue-9
Abstract : In this paper a FinFET based 8T SRAM design is presented on 22nm technology. This circuit is mainly governed
by the control switch CS, which is highly responsible for reduction in leakage current, thus resulting in a very low leakage
power of 0.331pW. Also, this design utilizes the functioning of a read buffer, which results in improved read delay of 0.16ns,
reduced read current of 4.838μA along with enhancing the Read Static Noise Margin (RSNM) with a value of 495mV, thus
enhancing the reading ability of the circuit and operating at a minimal voltage of 70mV. It also explains the energy
efficiency of the circuit in read and write modes, thus also greatly improving the average energy consumption of 1.2fJ of the
circuit.
Keywords - CMOS Integrated Circuits; Finfet; High Speed; Leakage Currents; Low Power; Nanotechnology; SRAM Cells;
Very Large Scale Integration (VLSI).
Type : Research paper
Published : Volume-5,Issue-9
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-9421
View Here
Copyright: © Institute of Research and Journals
|
 |
| |
 |
PDF |
| |
Viewed - 55 |
| |
Published on 2017-11-24 |
|