IJEEDC Performance Analysis Of Digital Communication System Using Matlab And Verilog HDL

Journal Paper

Paper Title :Performance Analysis Of Digital Communication System Using Matlab And Verilog HDL

Author :Surjeet Singh Kanawat, Anurag Singh

Article Citation :Surjeet Singh Kanawat ,Anurag Singh , (2016 ) " Performance Analysis Of Digital Communication System Using Matlab And Verilog HDL " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 1-6, Volume-4,Issue-5

Abstract : Matlab executions of binary amplitude shift keying (BASK), binary frequency shift keying (BFSK), and binary phase shift keying (BPSK) advanced modulators are displayed. The base number of squares important for accomplishing BASK, BFSK, and BPSK tweak, and for full mix with Matlab and HDL lessens BER (Bit Error Ratio). The data bearer signal and the bit stream (balancing sign) are client controllable. These advanced modulators were produced and aggregated to a Verilog Hardware Description Language (HDL) netlist, and were later actualized into an Isim. The usefulness of these computerized modulators was shown through reenactments utilizing the Isim and Modelsim (Vsim), and exploratory estimations of the continuous adjusted sign by means of a Matlab. Keywords- BASK; BFSK; BPSK; binary; digital modulator; amplitude shift keying; frequency shift keying; phase shift keying; OFDM Communication System.

Type : Research paper

Published : Volume-4,Issue-5


	\|		PDF	\|	Viewed - 132	\|	Published on 2016-05-25

Feb. 2025
Submitted Papers	:	80
Accepted Papers	:	10
Rejected Papers	:	70
Acc. Perc	:	12%
Issue Published	:	142
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No. of Authors	:	4938

Published : Volume-4,Issue-5

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