Paper Title :High Speed Low Power Asic Design Of Multiplier Using Vedic Mathematics
Author :Navyashree Hosamane, G.Jyothi, M Z Kurian
Article Citation :Navyashree Hosamane ,G.Jyothi ,M Z Kurian ,
(2015 ) " High Speed Low Power Asic Design Of Multiplier Using Vedic Mathematics " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 78-81,
Volume-3, Issue-7
Abstract : the performance of any processor will mainly depend upon its power and delay. The power and delay should be
less in order to get a high performance .Multipliers are the basic building blocks in almost all processors. Hence, there is a
need for highly efficient and sophisticated multiplier. The need of efficient multiplier is to increase the processing speed of
the system in real time signal and processing applications. A high speed low power multiplier design (ASIC) using Urdhva
and Nikhilam sutra ofVedic mathematics is presented in this paper. The proposed urdhva and nikilam multipliers achieve
60%, 77% improvement in speed and 37%, 50% improvement in power respectively, as compared with that of conventional
array multipliers.
Keywords: Vedicmultiplier; Arraymultiplier; Urdhva;Nikhilam
Type : Research paper
Published : Volume-3, Issue-7
DOI - 10.18479/ijeedc/2015/v3i7/48268
Copyright: © Institute of Research and Journals
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Published on 2015-07-04 |
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